The invention relates to electronic circuits requiring a voltage higher than a low supply voltage that powers these circuits. The invention is more particularly applicable to charge pump type voltage booster circuits used in chip cards.
An exemplary type of application of a circuit using a voltage higher than its low supply voltage is that of an integrated circuit including a non-volatile memory with floating-gate transistors. In these integrated circuits, a high voltage is needed to program and/or erase the memory. The programming and/or erasure of these memories requires a programming or erasure voltage of about 18 V, which is far higher than the low power supply voltage Vcc. The supply voltage Vcc may be about 3 V, for example. To avoid making the user provide the high voltage of 18 V, the integrated circuit is designed to have internal means for producing the high voltage from the low supply voltage Vcc. For this purpose, it is common practice to use a voltage booster circuit based upon the xe2x80x9ccharge pumpxe2x80x9d principle.
FIG. 1a is a schematic diagram of a known charge pump structure including a set of N series-connected elementary cells CE1 to CEN. Each elementary cell has two input terminals E1 and E2, two output terminals S1 and S2, and two clock input terminals CK1 and CK2. The high voltage HV is provided at the output terminal S1 of the Nth elementary cell. The clock inputs CK1 and CK2 of the elementary cells CE1 to CEN alternately receive four selection switch signals FN1, FN2, FX1 and FX2 produced by a control circuit 130 from a clock signal OSC. The control circuit 130 is powered by the supply voltage Vcc of the circuit. An oscillator 140 produces the clock signal OSC from the supply voltage Vcc. It is known in the art to make such an oscillator from inverters and filters. Yet, it is difficult to make a frequency-stable oscillator.
An elementary cell CE of the charge pump, illustrated in FIG. 1b, includes two transistors Ta and Tb and two capacitors Ca and Cb. A terminal of the capacitor Ca, the drain of the transistor Ta, and the drain of the transistor Tb are connected together to the input terminal E1. Similarly, the control gate of the transistor Ta, the source of the transistor Tb, and a terminal of the capacitor Cb are connected together to the input terminal E2. The source of the transistor Ta and the control gate of the transistor Tb are connected respectively to the output terminals S1 and S2. Finally, the other terminal of the capacitor Ca and the other terminal of the capacitor Cb are connected respectively to the clock input terminals CK1 and CK2. In practice, the capacitors Ca and Cb are each made from transistors whose control gates correspond to a terminal of the capacitors and whose drains and sources, which are connected together, correspond to the other terminal of the capacitors.
The selection switch signals FN1, FN2, FX1 and FX2 are shown in FIG. 1c. The first and third selection switch signals FN1 and FX1 are two complementary selection switch signals but are not overlapping in the high state. They switch between two values, which are substantially 0 and a first voltage level VA. The second and fourth selection switch signals FN2 and FX2, which are not overlapping in the high state, are signals respectively synchronized with the first and third selection switch signals FN1, FX1. They switch between two values, which are substantially 0 and a second voltage value VB.
Assuming that the selection switch signals FN1 and FN2 are initially at VA and VB and that the selection switch signals FX1 and FX2 are initially at 0 V, the selection switch signals FN1, FN2, FX1 and FX2 are such that: the falling of the signal FN2 to 0 V leads to the falling of the signal FN1 to 0 V; the falling of the signal FN1 to 0 V leads to the rising of the signal FX1 to VA; the rising of the signal FX1 to VA leads to the rising of the signal FX2 to VB, which falls back to 0 V after a period of time; the falling of the signal FX1 to 0 V leads to the rising of the signal FN1 to VA; and the rising of the signal FN1 to VA leads to the rising of the signal FN2 to VB.
With the high voltage HV being obtained, the working time and the losses of the charge pump, as well as the total energy that it consumes to give the voltage HV, essentially depend on a number of factors. These factors are the number N of elementary cells, the supply voltage Vcc, and the threshold voltage VT of the transistors Ta, Tb used and the voltage levels VA, VB. Of course, it is desirable to obtain a sufficiently high voltage HV without excessively increasing the number N of elementary cells used. To do so, it is the general practice to choose a voltage level VA that is equal to the supply voltage Vcc and a voltage level VB that is as high as possible. The voltage level VB depends, inter alia, on the number N of elementary cells and on the maximum voltage to be allowed to go through the transistors TA, TB. The value of VB must be limited to not disrupt the gate oxides of the transistors. Yet, in practice, the control circuits do not provide for a voltage level VB higher than twice the supply voltage Vcc.
The problem of the total consumption of energy from the charge pump is vital particularly for applications known as contactless applications. In such application, the total energy is given remotely by a reader in the form of a radio frequency signal. The energy received by the card is limited and greatly decreases when the distance between the reader and the card increases. If it is desired to use the card at a reasonable distance from the reader, then it is necessary to limit the total energy consumption of the charge pump type voltage booster circuits used in contactless applications.
To this end, the invention proposes an integrated circuit card receiving power in the form of a radio frequency signal. The integrated circuit card may include a voltage generator that produces a first power supply voltage and a voltage booster circuit. The voltage booster circuit receives the first power supply voltage at a first supply input terminal thereof, receives a second power supply voltage higher than the first power supply voltage at a second supply input terminal thereof, and produces a high voltage.
According to one embodiment, the voltage generator may include a detection and rectifier circuit that receives the radio frequency signal and produces a rectified voltage at an output terminal thereof. A first regulator may receive the rectified voltage at a supply input terminal thereof and produce the first supply voltage. The second supply input terminal of the voltage booster circuit may be connected to the power supply input terminal of the first regulator, where the second power supply voltage is equal to the rectified voltage.
The integrated circuit card may also include a second regulator with an input terminal connected to the output terminal of the detection and rectifier circuit to receive the rectified voltage and an output terminal connected to the power input terminal of the first regulator. The second regulator receives the rectified voltage and produces the second power supply voltage, and the first regulator receives the second power supply and produces the first power supply voltage.
The voltage booster circuit may include a control circuit that produces at least one pair of selection switch signals. The first selection switch signal may oscillate between a zero voltage and a first voltage level, and the second selection switch signal may oscillate between a zero voltage and a second voltage level. The control circuit may receive the first and second power supply voltages. Also, the first and second voltage levels may be obtained respectively from the first and second power supply voltages.
The voltage booster circuit may further include N series-connected elementary cells for producing the high voltage. The N elementary cells may be controlled by the at least one pair of selection switch signals. The control circuit may include a phase separation circuit that receives a clock signal and a first supply voltage and produces a first selection switch signal.
The control circuit may also include at least one raising circuit that receives a first selection switch signal and the first and second supply voltages and produces the second selection switch signal by raising the level of the first selection switch signal. The phase separation circuit may also produce at least one logic signal representing the logic state of the first selection switch signal. The N elementary cells may be driven either by at least one pair of selection switch signals or by the first selection switch signal and the at least one logic signal. Furthermore, the integrated circuit card may include a clock signal generator that receives the radio frequency signal and produces the clock signal.
The invention thus proposes the use of two different power supply voltages to supply one charge pump which consumes, on the whole, less energy and also for a shorter period. Indeed, by using two power supply voltages, one of which is higher than the other, the invention increases the level of voltage reached by the selection switch signals. As a result, the voltage applied to the gates of the transistors of the elementary cells of the charge pump is increased. The desired high voltage HV is thus obtained quicker, and the total energy consumption is reduced. The number of elementary cells may be reduced, thus bringing about a corresponding reduction in the total size in terms of silicon surface area of the voltage booster circuit. Furthermore, by using two power supply voltages, the power consumed by the charge pump is distributed between two voltage sources which produce them. Thus, the risk of a collapse of either of these sources is reduced.
The invention is particularly useful for integrated circuit cards where it is easy to obtain two voltages from a single radio frequency signal received by the card. For example, for a chip card at about 50 cm from a reader, using present-day solutions and with a voltage supply Vcc of about 3 V, the charge pump consumes energy for about 50 xcexcs to give a high voltage HV of about 18 V. The charge pump of the invention, by using two supply voltages (e.g., a 3 V supply and a 5 V supply) consumes energy for only about 10 xcexcs and produces a high voltage HV of about 18 V. Furthermore, this is accomplished without reducing the distance between the reader and the chip card.
Another advantage of the invention is that it eliminates the oscillator commonly used to give the clock signal. For this purpose, the invention uses a clock signal generator which, from a radio frequency signal with a frequency f0 received by the card, produces a clock signal with a frequency f=f0/p, where p is an integer. Conventionally, the frequency f0 is equal to 13.56 MHZ. A clock signal generator of this kind has the advantage of giving a clock signal that is particularly stable in frequency, inasmuch as the frequency f0 of the radio frequency signal received by the card is stable. This approach reduces the problems of frequency stability found in the commonly used oscillator. According to the present invention, the circuits of the charge pump no longer need to be sized to account for the variable frequency clock signals. This reduces the total size (in terms of silicon surface area) of the charge pump.
Furthermore, with a clock signal generator of this kind it is possible to reduce the frequency of the clock signal by choosing a number p greater than 1, for example equal to 8 (giving a clock signal with a frequency f=1.7 MHZ). This further reduces the total energy consumption of the charge pump.